3-input arithmetic logic unit

ABSTRACT

A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified opcode, a first 3-to-2 compressor for receiving a respective least significant bit of said operands or its complement, and a Half Adder coupled to the first 3-to-2 compressor and responsive to an output thereof and to said opcode for outputting a least significant bit of a sum equal to A+B+C or A+B−C or A−B+C or A−B−C. A plurality of 3-to-2 compressors each in respect of remaining bits of the operands receive a respective bit of the operands or its complement, and a 2-input adder coupled to the 3-to-2 compressors receive respective carry and save outputs thereof and computing respective bits of the sum apart from the least significant bit.

FIELD OF THE INVENTION

[0001] This invention relates to arithmetic units particularly used forDigital Signal Processing.

BACKGROUND OF THE INVENTION

[0002] In many advanced applications, Digital Signal Processing (DSP) isrequired, usually when analog and digital systems meet. Increasing thenumber of operands being used in each calculation increases the datacomputation rate. Thus, the standard 2-input Adder can add two operandswhile the 3-input Adder can add three operands, increasing the datacomputation rate by a factor of 50%.

[0003] One of the main tasks of DSP is the summation of multiplicationoperations:

ΣAi*Xi

[0004] In order to execute such tasks a Multiply and Accumulate (MAC)Unit is used, which also requires a multiplier and adder. The trend inDSP implementation is to increase the number of MAC Units in order toincrease the data computation rate. The 3-input AU can be used in suchcases and has several advantages.

[0005] In the case where the products of two multipliers should besummed, the 3-input arithmetic unit illustrated in FIG. 1b canaccumulate the result more easily than two separate 2-input Addersillustrated in FIG. 1a, thus requiring only one accumulator instead oftwo.

[0006] In other applications such as complex multiplication, the 3-inputAU can increase data computation rates. Complex multiplication is veryimportant and is used in many applications such as FFT (Fast FourierTransform), which is very commonly used in many DSP applications. Themultiplication of two complex numbers A and B is computed as follows:

Σ(Ar+i*Ai)*(Br+i*Bi)=Σ[(Ar*Br−Ai*Bi)+i*(Ar*Bi+Ai*Br)]

[0007] In order to implement such a task, the real and imaginary partshave to be calculated separately. In each calculation, two multipliersare needed as well as a single 3-input AU in order to accumulate themultipliers result, as shown in FIG. 1a.

[0008] As is known, when an adder is used to subtract a second operandfrom a first operand, this is done by adding to the first operand thetwos complement of the second operand. This, in turn, is achieved byinverting each bit in the second operand and adding “1”, thus, ineffect, requiring an additional adder, and increasing the computationtime because each adder imposes its own computing overhead. The problemis further compounded when second and third operands are successivelysubtracted from a first operand, i.e. A−B−C. In this case, the twocomplements of both B and C must be derived by inverting each operandand adding two “1”s, thus requiring in total five adders, and evenfurther increasing the computation overhead.

[0009] It would therefore be of particular benefit to provide a 3-inputadder for inputting three operands A, B and C and being capable ofcomputing A−B−C without requiring additional adder stages, since thiswould decrease the computing overhead and increase computation speed.

[0010] It would be of further benefit to configure such a 3-input adderto implement split operand arithmetic so as more efficiently to carryout complex arithmetic, as explained above.

SUMMARY OF THE INVENTION

[0011] It is therefore a principal object of the present invention toprovide a 3-input adder for inputting three operands A, B and C andbeing capable of computing A−B−C without requiring additional adderstages

[0012] It is a further object of the invention configure such a 3-inputadder to implement split operand arithmetic so as more efficiently tocarry out complex arithmetic.

[0013] These objectives are realized in accordance with the invention bya 3-input adder/subtractor unit, comprising:

[0014] a first input for receiving a first operand A,

[0015] a second input for receiving a second operand B,

[0016] a third input for receiving a third operand C,

[0017] an add/subtract unit having a control input for receiving auser-specified opcode and a 2-input carry save adder in respect of eachbit of said operands for receiving a respective bit of the firstoperand, the second operand or its complement and the third operand orits complement, said add/subtract unit being responsive to said opcodefor producing an output equal to A+B+C or A+B−C or A−B+C or A−B−C.

[0018] According to a further aspect of the invention there is provideda hardware-implemented method for computing a sum of three operands A, Band C, said method comprising:

[0019] (a) providing a user-specified opcode for indicating that the summust be equal to A+B+C or A+B−C or A−B+C or A−B−C,

[0020] (b) computing a least significant bit of the sum and propagatinga carry bit thereof through a chain of 3-to-2 compressors each inrespect of remaining bits of said operands for receiving a respectivebit of said operands or its complement, and producing respective carryand save output pairs, and

[0021] (c) summing the respective carry and save output pairs forcomputing respective bits of said sum apart from the least significantbit.

[0022] The invention provides an improved AU architecture that supportsfour arithmetic operations between three user-defined operands. The fourarithmetic operations are add, add-sub, sub-add and sub-sub.

[0023] Furthermore, the same architecture implements split instructionsbetween two operands using the same hardware without overhead.

[0024] The 3-Input AU according to the invention allows DSPs to executeparallel instructions in one given machine cycle in Normal Mode or SplitMode.

[0025] The main features of the 3-input AU according to the inventioncan be summarized as follows:

[0026] Split Mode, add/sub low and high part of two operandsindependently.

[0027] Twos-Complement Arithmetic.

[0028] Can be implemented in N bits word width.

[0029] Technology Independent

[0030] The 3-input AU according to the invention has a simple controlsignal (OpCode) issued by the user. This signal is used to select theoperand in an Add instruction and the inverted operand in asub-instruction, the selected value being issued to the Add/Sub Unit.

[0031] The Add/Subtract Unit employs 3-to-2 Carry Save Adders (CSA) tocompress the three input to two vectors (a Sum Vector and a CarryVector). A conditional sum with a Carry Look Ahead mechanism is used tosum the two vectors.

[0032] In split mode, carry out from the low part is ignored by the highpart, and the carry vector (shown as 16C in FIG. 3) is forced to zero.

[0033] The implementation described at the Logic Level can be fabricatedin CMOS, Bipolar or other technologies.

[0034] The AU (Arithmetic Unit) performs the following operationaccording to the Op Code issued by the user. TABLE I Cin Cin noteOperation high low Split (i)Op Code Add-Add (a)A + B + C 0 0 0 0 0 0 0Add-Sub A + B − C 0 1 0 0 0 1 1 Sub-Add A − B + C 0 1 0 1 1 0 0 Sub-SubA − B − C 0 1 0 1 1 1 1 C = ‘0’ Ah + Bh; Al + Bl 0 0 1 1 1 X X C = ‘0’Ah + Bh; Al − Bl 0 0 1 0 1 X X C = ‘0’ Ah − Bh; Al + Bl 1 0 1 1 0 X X C= ‘0’ Ah − Bh; Al − Bl 1 1 1 1 1 X X B = ‘0’ Ah + Ch; Al + Cl 0 0 1 X X0 0 B = ‘0’ Ah + Ch; Al − Cl 0 1 1 X X 1 0 B = ‘0’ Ah − Ch; Al + Cl 1 01 X X 0 1 B = ‘0’ Ah − Bh; Bl − Cl 1 1 1 X X 1 1

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to understand the invention and to see how it may becarried out in practice, a preferred embodiment will now be described,by way of non-limiting example only, with reference to the accompanyingdrawings, in which:

[0036]FIGS. 1a and 1 b are block diagrams showing functionally SummingMultipliers using Dual MAC Units with 2-and 3-input arithmetic units,respectively;

[0037]FIG. 2 is a block diagram showing schematically the 3-inputarithmetic unit of FIG. 1b;

[0038]FIG. 3 is a schematic representation showing an implementation ofa 32 bit 3-input Add/Subtract Unit for use in the 3-input arithmeticunit shown in FIG. 2;

[0039]FIGS. 4a and 4 b are schematic representations showingimplementations of a Full Adder used as a 3-2 Compressor in theAdd/Subtract Unit of FIG. 2; and

[0040]FIGS. 5a and 5 b are schematic representations showingimplementations of a Half Adder used in the Add/Subtract Unit of FIG. 2.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0041]FIG. 2 shows schematically a 3-Input AU depicted generally as 20having first, second and third inputs 21, 22 and 23 for feeding theretorespective first, second and third operands, A, B and C. The firstoperand A is fed directly to an Add/Sub Unit 24 since none of theoperations uses the twos complement of A. The second and third operandsB and C, respectively, are both split into high components B (high) andC (high) and into low components B (low) and C (low). Most typically,the operands are words having a defined number of bits, e.g. 32. In suchcase, the high component is the 16 most significant bits and the lowcomponent is the 16 least significant bits. The high and low componentsof the second operand B are inverted by respective inverters 25 and 26so as to produce their respective complements {overscore (B)} (high) and{overscore (B)} (low) whilst the high and low components of the thirdoperand C are inverted by respective inverters 27 and 28 so as toproduce their respective complements {overscore (C)} (high) and{overscore (C)} (low). For the sake of simplicity, FIG. 2 shows theoperations performed on the operands per se. In fact, the operations areperformed on each bit of the first operand A and on each bit of the highand low components of the second and third operands B and C and on theirrespective complements {overscore (B)} and {overscore (C)}. The fullbit-by-bit implementation for a 32-bit adder is explained in greaterdetail below with reference to FIG. 3 of the drawings.

[0042] The high and low components of the second operand B as well astheir respective complements are fed to respective 2-to-1 multiplexers29 and 30 each having a respective control input 31 and 32, whichcontrols whether the output of the respective multiplexer 29 and 30 isthe high and low component of B or the high and low component of{overscore (B)}. Likewise, high and low components of the third operandC as well as their respective complements are fed to respective 2-to-1multiplexers 33 and 34 each having a respective control input 35 and 36,which controls whether the output of the respective multiplexer 33 and34 is the high and low component of C or the high and low part of{overscore (C)}.

[0043] In order to achieve high speed, the controls to the respectivemultiplexers 29, 30, 33 and 34 are issued directly using an Op Codewithout a Decode stage. Table II below lists conversions from the OpCode to the controls: Table II Value Control Opcode[0] Control1 (36)Opcode[1] Control2 (35) Opcode[2] Control3 (32) Opcode[3] Control4 (31)

[0044] Two carries are input to the Add/Sub Unit 24, designatedCarry-in-low 40 and a Carry-in-high 41. In full width operation theCarry-in-low is used as carry in and the Carry-in-high is ignored. ASplit Mode control 42 may also be fed to the Add/Sub Unit 24 whereby theCarry-in-low is used as carry in for the low component and Carry-in-highis used as carry in for the high component. This is explained in greaterdetail below with reference to FIG. 3 of the drawings.

[0045] With this architecture, the Add/Sub Unit 24 can support a SplitMode option and implement the high speed 3-Input Adder.

[0046] The inputs issued to the Add/Sub unit 24 are:

[0047] (i) Three inputs a, b and c designated respectively 43, 44 and 45for feeding thereto the operands A, B and C, or A, {overscore (B)} and Cor A, B and {overscore (C)} according to the specified opcode asdescribed in Table I.

[0048] (ii) Carry-in-low 40 used as carry in during full width operationand carry in to the low part in Split Mode operation.

[0049] (iii) Carry-in-high 41 used as carry in to the high part in SplitMode operation.

[0050] (iv) Split Mode Control 42 set to HIGH in Split Mode and to LOWin Full width Mode.

[0051] The outputs from the Add/Sub Unit 24 are:

[0052] (i) 32 bit data output designated 46.

[0053] (ii) Carry-out-high designated 47 (the carry out in summation of3 input binary words is 2 bit).

[0054] (iii) Carry-out-low designated 48, carry out of the low part inSplit Mode—the data is valid only in Split Mode

[0055] Add/Sub Unit

[0056]FIG. 3 shows an actual implementation of the Add/Sub Unit 24having 32 bits. In the following description, numerous specific details,such as the number of bits, are provided by way of non-limiting exampleonly to enable a thorough understanding of the invention. The Add/SubUnit 24 can be implemented with a ripple Carry Adder, Carry Look Aheador any other 2-Input Adder, although preferably a Carry Look Ahead adderis used so as to achieve best timing performance.

[0057] Also, as seen in FIG. 3, a conditional sum is used to achieve thebest timing performance the invention. The Add/Sub Unit 24 employs3-to-2 Carry Save Adders (CSA) to compress the three bits derived fromeach bit of the three input operands A, B and C to only two operands. Inthe figure, the Least Significant Bit of the low component of each ofthe operands is fed to a CSA 50, the next Least Significant Bit of thelow component of each of the operands is fed to a CSA 51, and so on.Likewise, the Least Significant Bit of the high component of each of theoperands is fed to a CSA 52, the next Least Significant Bit of the highcomponent of each of the operands is fed to a CSA 53, and so on. EachCarry Save Adder generates a Carry Vector and Sum Vector. The lowcomponents of these two vectors are added by a first 2-input adder 54and the high components of the two vectors are added by a conditionalsum and a second 2-input adder 55 and a third 2-input adder 56. Thesecond and third 2-input adders 55 and 56 have identical functionality,their only difference being that their carry-in bits are setrespectively to ‘1’ and ‘0’ according to the selected Op Code. Thus,denoting the first bit of each of three operands as A₀, B₀ and C₀,respectively, the first 3-to-2 Carry Save Adder 50 receives these bitsA₀, B₀ and C₀ and produces at respective outputs a Carry bit and a Sumbit. The Carry and Sum bits from each of the Carry Save Adders apartfrom the first are added by the first 2-input adder 54 or the second andthird 2-input adders 55 and 56.

[0058] The first stage in the Add/Sub Unit 24 compresses the threeinputs to two vectors: a Carry Vector and a Sum Vector. Standard FullAdder Cells are employed as shown in FIG. 3, their implementation beingas shown in FIG. 4b. Each cell constituted by a respective Full Adderreceives a three input signal and provides an Output Sum Signal and aCarry Out Signal. The sum signal is presented by equation (1):

S=a{circle over (×)}b{circle over (×)}c  (1)

[0059] where a and b are the data inputs, c is the carry in, and thesign{circle over (×)} stands for Exclusive OR.

[0060] The carry out of the Full Adder is presented by equation (2):

Co=a·b+c·(a+b)  (2)

[0061] where the sign · stands for logic AND and the sign + stands forlogic OR.

[0062] The second stage is to sum the Carry Vector and the Sum Vector.The carry vector is shifted one bit left prior to inputting to the first2-input adder 54. Thus, it is seen from FIG. 3 that the leastsignificant carry output derived from the sum of A0, B0 and C0 is fed tothe a₀ input of the first 2-input adder 54, where it is added to the sumof A1, B1 and C1 fed to the b₀ input thereof. This is expressedmathematically in equation (3):

Out[n]=S[n+1]+C[n]  (3)

[0063] The Add/Sub Unit 24 supports four combinations as described inTable I. Using twos-complement arithmetic the sum of the fourcombinations can be described by the equations (4), (5), (6) and (7).

Sum=A+B+C  (4)

Sum=A−B+C=A+{overscore (B)}+1+C  (5)

Sum=A+B−C=A+B+{overscore (C)}+1  (6)

Sum=A−B−C=A+{overscore (B)}+1+{overscore (C)}+1  (7)

[0064] All four forms of the combinations described by equations (4) to(7) can be summarized by equation (8):

Sum=A+b+α+c+β  (8)

[0065] Where:

[0066] b=B or {overscore (B)}, c=C or {overscore (C)} and α and β can be1 or 0 (zero extended to n bit).

[0067] To implement the addition contemplated by equation (8) with CarrySave Adders conventionally requires the use of 5-to-2 CSA compressorshaving the following inputs:

[0068] a(n) . . . a(1) a(0)

[0069] b(n) . . . b(1) b(0)

[0070] 0 . . . 0 α

[0071] c(n) . . . c(1) c(0)

[0072] 0 . . . 0 β

[0073] Since α and β are constant (1 or 0), α+β will also be constantand can be set to all the combinations as shown below in Table III:TABLE III α β α + β A + B + C 0 0 00 A − B + C 0 1 01 A + B − C 1 0 01 A− B − C 1 1 10

[0074] Letting i be the MSB and j the LSB in (α+β), the summation with iand j is illustrated as follows with further reference to FIG. 3 of thedrawings.

[0075] i and j are fed to the Add/Sub Unit 24 from the Op Code fed tothe arithmetic unit 20 as listed in Table II and shown in FIG. 2. Thus,it is seen that according to the invention, when using i and j, 4-to-2compressors are needed, since the carry is propagated and the criticalpath is not in the LSB. This is an improvement over the conventionalapproach where as noted above the addition contemplated by equation (8)is implemented with Carry Save Adders requiring the use of 5-to-2 CSAcompressors. The least significant row is summed by the Full Adder 50and a Half Adder 57, Sum[0] being the output of the Half Adder 57without any further manipulation being required. Since the carry vectoris shifted one bit left, the carry out of the Full Adder 50 is fed tothe 2-input adder 51 via its a₀ input.

[0076] The second row (LSB+1) A[1], B[1] and C[1] are compressed by the3-to-2 compressor 51 and fed to the 2-input adder 54. The carry in tothe 2-input adder 54 can be either i or the carry out of the Half Adder57.

[0077] The principle of a conditional sum implemented in the high bytesecond 2-input adder 55 calculates the high byte of the sum under theassumption that the carry in (to the 2-input adder 55) is ‘1’ andproduces at its output a provisional sum sumA. Likewise, the third2-input adder 55 calculates the high byte of the sum under theassumption that the carry in (to the 2-input adder 56) is ‘0’ andproduces at its output a provisional sum, sumB. A 2-to-1 Multiplexer 58selects between the provisional sums sumA and sumB calculated by the2-input adders 55 and 56 according to the control as well as the carryout high. Specifically, if the control is high sumA-carryA is selectedas output; if the control is low sumB, carryB is selected.

[0078] The control to the Multiplexer 58 generates three signals:

[0079] 1. Carry out low (carry out of CLA block).

[0080] 2. Carry in high (issued by the user).

[0081] 3. Split Mode indication (issued by the user).

[0082] In Full width Mode the control is equal to the carry out lowissued from the low part, in Split Mode the control is equal to thecarry in high input to the unit.

[0083] Basic Cells

[0084] Full Adder (3-to-2 Compressor):

[0085]FIG. 4a shows symbolically the Full Adder used as a 3-to-2compressor in the Carry Save Adder, whose Truth Table is a shown below:FIG. 4b shows how the Full Adder is implemented using standard logicelements. Truth Table S Co Ci B A 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 10 1 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 1 1 1 1

[0086] Half Adder

[0087]FIG. 5a shows symbolically the Half Adder, whose Truth Table is ashown below: FIG. 5b shows how the Half Adder is implemented usingstandard logic elements. Truth Table S Co B A 0 0 0 0 1 0 0 1 1 0 1 0 01 1 1

EXAMPLES

[0088] In order to understand the invention, some examples will now bedescribed showing how the 3-Input AU 20 performs various arithmeticoperations on three operands A=111, B=101 and C=011:

[0089] 1. A+B+C

[0090] i=0,j=0 (as shown in Table III)

[0091] A0=1

[0092] B0=1

[0093] C0=1

[0094] S[0]=1 (from Least Significant 3-to-2 Adder) passed to the H.Aand since j=0, sum[0]=1 and C_(out)=0 (Carry out from Half Adder 57 is 0since j=0). Cin=0 since both C_(out) and i are 0. This gives:

[0095] a0=1

[0096] Cin=0

[0097] A1=1

[0098] B1=0

[0099] C1=1

[0100] b0=0

[0101] a1=1

[0102] A2=1

[0103] B2=1

[0104] C2=0

[0105] b1=0

[0106] a2=1

[0107] As explained above, the Adder 54 sums each of the two same-orderbits so as to produce corresponding bits of the sum, displaced by onebit to the left. The zero order output is not generated by the Adder 54,but rather is equal to the Sum[0] output of the half adder 57. The sumis therefore represented as follows:

Sum[0]=S output of the half adder 57

Sum[1]=a ₀ +b ₀

Sum[2]=a ₁ +b ₁

Sum[3]=a ₂ +b ₂

[0108] where:

[0109] a₀=1

[0110] b0=0

[0111] a1=1

[0112] b1=0

[0113] a₂=1

[0114] b₂=0 (not defined)

[0115] This gives:

Sum[0]=1

Sum[1]=a ₀ +b ₀=1

Sum[2]=a ₁ +b ₁=1

Sum[3]=a ₂ +b ₂=1

[0116] So the value of A+B+C is 1111, which is correct.

[0117] 2. A−B+C

[0118] i=0,j=1 (as shown in Table III)

[0119] A0=1

[0120] {overscore (B0)}=0

[0121] C=1

[0122] S[0]=0 (from Least Significant 3-to-2 Adder) passed to the H.Aand since j=1, sum[0]=S[0]+j=1 and C_(out)=0 (Carry out from Half Adder57 is 0 since one input, S[0], is 0). Cin=0 since both C_(out) and i are0. This gives:

[0123] a0=1

[0124] Cin=0

[0125] A1=1

[0126] B1=0

[0127] C1=1

[0128] b0=0

[0129] a1=1

[0130] A2=1

[0131] {overscore (B2)}=0

[0132] C2=0

[0133] b1=1

[0134] a2=0

[0135] As explained above, the Adder 54 sums each of the two same-orderbits so as to produce corresponding bits of the sum, displaced by onebit to the left. The zero order output is not generated by the Adder 54,but rather is equal to the Sum[0] output of the half adder 57. The sumis therefore represented as follows:

Sum[0]=S output of the half adder 57

Sum[1]=a ₀ +b ₀

Sum[2]=a ₁ +b ₁

Sum[3]=a ₂ +b ₂

[0136] where:

[0137] a₀=1

[0138] b₀=0

[0139] a₁=1

[0140] b₁=1

[0141] a2=0

[0142] b₂=0 (not defined)

[0143] This gives:

Sum[0]=1

[0144] Sum[1]=a ₀ +b ₀=1

Sum[2]=a ₁ +b ₁=0

Sum[3]=a ₂ +b ₂=0

[0145] So the value of A−B+C is 0011, which is correct.

1. A 3-input adder/subtractor unit, comprising: a first input forreceiving a first operand A, a second input for receiving a secondoperand B, a third input for receiving a third operand C, and anadd/subtract unit including: a control input for receiving auser-specified opcode, a first 3-to-2 carry-save adder for receiving arespective least significant bit of said operands or its complement, aHalf Adder coupled to the first 3-to-2 carry-save adder and responsiveto an output thereof and to said opcode for outputting a leastsignificant bit of a sum equal to A+B+C or A+B−C or A−B+C or A−B−C, aplurality of 3-to-2 carry-save adders each in respect of remaining bitsof said operands for receiving a respective bit of said operands or itscomplement, and a 2-input adder coupled to all of said 3-to-2 carry-saveadders for receiving respective carry and save outputs thereof andcomputing respective bits of said sum apart from the least significantbit.
 2. The 3-input adder/subtractor unit according to claim 1, whereinat least one of the first, second and third operands is a single bit. 3.The 3-input adder/subtractor unit according to claim 1, wherein at leastone of the first, second and third operands is a word comprisingmultiple bits.
 4. The 3-input adder/subtractor unit according to claim3, wherein the 2-input adder comprises: a first 2-input adder having aplurality of inputs each coupled to a respective one of the 2-inputcarry save adders for summing a low component of said output, a second2-input adder having a carry-in bit set to ‘1’ and having a plurality ofinputs each coupled to a respective one of the 2-input carry save addersfor summing a first high component of said output, a third 2-input adderhaving a carry-in bit set to ‘0’ and having a plurality of inputs eachcoupled to a respective one of the 2-input carry save adders for summinga second high component of said output, and a multiplexer coupled torespective outputs of the second and third 2-input adders and beingresponsive to the opcode for selecting the first or second highcomponents.
 5. The 3-input adder/subtractor unit according to claim 1,wherein the add/subtract unit is responsive to said opcode being set toa split mode opcode for outputting a low byte component of the sum at anoutput of the first 2-input carry save adder and for outputting a highbyte component of the sum at an output of the second and third 2-inputcarry save adders.
 6. A hardware-implemented method for computing a sumof three operands A, B and C, said method comprising: (a) providing auser-specified opcode for indicating that the sum must be equal to A+B+Cor A+B−C or A−B+C or A−B−C, (b) computing a least significant bit of thesum and propagating a carry bit thereof through a chain of 3-to-2compressors each in respect of remaining bits of said operands forreceiving a respective bit of said operands or its complement, andproducing respective carry and save output pairs, and (c) summing therespective carry and save output pairs for computing respective bits ofsaid sum apart from the least significant bit.